Method and system to preprogram and predict the next microcode address

ABSTRACT

A microprocessor includes a first memory to store microcode and a second memory to store predicted micro-operation addresses. Micro-operation addresses are predicted, stored in memory, and retrieved to get the next micro-operations from the microcode memory. Misprediction recovery logic is used to determine if the next predicted address is correct and to determine a recovery address to correct the predicted address if the predicted address is incorrect.

BACKGROUND OF THE INVENTION

[0001] 1. Field of the Invention

[0002] The present invention relates to the field of micro-code branchprediction. In particular, the present invention relates topreprogramming and predicting the address of the next microcodeinstruction to be executed.

[0003] 2. Description of Related Art

[0004] Predicting branches in micro-code increases performance of themicroprocessor. Branch prediction involves determining the next addressto look up and then using that address to access the read-only memory(ROM) where the micro-code instruction is stored. Various methods areused to determine the next address to look-up in the micro-code ROM. Inany case, after the next address is determined, the micro-code ROM isaccessed at that address to get the micro-operations (uops). Therefore,no matter how the address determination logic is improved to decreasethe time for an address look-up, performance is still limited by theaccess time of the ROM. As the size of the micro-code increases, theaccess time of the ROM increases. As clock frequencies increase, it maytake more than one clock cycle to access the micro-code ROM, whichcauses the instruction pipeline to stall while waiting for the nextuops. Therefore, as processors utilize a larger micro-code and clockfrequencies increase, limiting performance of a look-up to the accesstime of the micro-code ROM becomes an increasing problem.

BRIEF DESCRIPTION OF DRAWINGS

[0005] The invention is illustrated by way of example, and not by way oflimitation, in the figures of the accompanying drawings in which likereference numerals refer to similar elements.

[0006]FIG. 1 is a block diagram illustrating one embodiment of theinvention.

[0007]FIG. 2 illustrates an example implementation of the mispredictionrecovery logic according to one embodiment of the invention.

[0008]FIG. 3 is a flow chart illustrating an embodiment of theinvention.

DETAILED DESCRIPTION OF THE INVENTION

[0009] Embodiments of a system and method for preprogramming andpredicting the next microcode address are described. In the followingdescription, numerous specific details are provided, for a thoroughunderstanding of embodiments of the invention. One skilled in therelevant art will recognize, however, that the invention can bepracticed without one or more of the specific details, or with othermethods, components, materials, etc. In other instances, well-knownstructures, materials, or operations are not shown or described indetail to avoid obscuring aspects of the invention.

[0010] Reference throughout this specification to “one embodiment” or“an embodiment” means that a particular feature, structure, orcharacteristic described in connection with the embodiment is includedin at least one embodiment of the present invention. Thus, theappearances of the phrases “in one embodiment” or “in an embodiment” invarious places throughout this specification are not necessarily allreferring to the same embodiment. Furthermore, the particular features,structures, or characteristics may be combined in any suitable manner inone or more embodiments.

[0011] Referring to FIG. 1, a block diagram illustrates a system 100according to one embodiment of the invention. Those of ordinary skill inthe art will appreciate that the system 100 may include more componentsthan those shown in FIG. 1. However, it is not necessary that all ofthese generally conventional components be shown in order to disclose anillustrative embodiment for practicing the invention. System 100includes a memory to store microcode 102, a memory to store predictedaddresses 104, misprediction recovery logic 106, and a selector 108. Inone embodiment, the selector 108 is a multiplexer (MUX). In oneembodiment, the memory to store microcode 102 is a read-only memory(ROM). The microcode memory 102 stores micro-operations (uops). When thememory 102 is accessed at a next address 114, it will output the uops116 stored at that address line. There may be one or more uops stored atan address line. The uops 116 output from the microcode memory 102 maybe used in an instruction pipeline in a microprocessor. In oneembodiment, the uops are stored in a register to be used in theinstruction pipeline.

[0012] Addresses that will be used to access the microcode memory 102are predicted and then stored in memory 104. In one embodiment, theaddresses are predicted based on the uops in the microcode. In oneembodiment, the memory 104 is a ROM. When uops are needed by theinstruction pipeline, they are retrieved by accessing the microcodememory 102 at the addresses retrieved from the predicted addressesmemory 104. Misprediction recovery logic 106 is used to determine if thepredicted address 110 retrieved from memory 104 is a correct nextaddress at which to access the microcode memory 102. If the predictedaddress 110 is correct, the misprediction recovery logic 106 will outputa MUX select 118 that selects the predicted address 110 as the nextaddress 114 at which to access the microcode memory 102. If themisprediction recovery logic 106 determines that the predicted address110 is incorrect, then it will correct the predicted address bydetermining a recovery address 112 and outputting a MUX select 118 thatselects the recovery address 112 as the next address 114 at which toaccess the microcode memory 102. For example, the misprediction recoverylogic may output a MUX select of 0 when the predicted address is correctand output a MUX select of 1 when the predicted address is incorrect.Therefore, MUX 108 will select the predicted address as the next addresswhen the MUX select is 0. With a MUX select of 1, MUX 108 will selectthe recovery address as the next address.

[0013] Referring to FIG. 2, an example implementation of themisprediction recovery logic 106 according to one embodiment of theinvention is illustrated. The misprediction recovery logic 106 has twoinputs: the next address 114 and the uops 116. The mispredictionrecovery logic 106 has two outputs: the recovery address 112 and the MUXselect 118. The MUX select 118 indicates whether the predicted address110 is correct and if so, selects the predicted address 110 as the nextaddress 114 at which to access the microcode ROM 102. The recoveryaddress 112 is used as the next address to access the microcode ROM 102when the predicted address 110 is determined to be incorrect.

[0014] To determine whether the predicted address 110 is correct, themisprediction recovery logic 106 compares whether there is a jumppresent and whether a jump was executed. In one embodiment, each uop hasa plurality of bits, including a jump bit. The jump bit indicateswhether the uop is a jump. For example, the jump bit may be a 1 when theuop is a jump and a 0 when the uop is not a jump. In the example shown,there are four uops stored at each address line in the microcode memory102, and each uop includes one jump bit. Therefore, there are a total offour jump bits. In one embodiment, the uops 116 are stored in a register232 to be used by the misprediction recovery logic 106. In the exampleshown, the four jump bits are input into an OR gate 208 to determine ifthere is a jump present 200.

[0015] In one embodiment, the next address 114 is stored in registers234 and 236 for use by the misprediction recovery logic 106. The nextaddress 114 has a plurality of bits. The two least significant bits(Isb) of the next address are used as the selector for four MUXes 224,226, 228, and 230. The inputs to MUX 224 are 1, 0, 0, 0. The inputs toMUX 226 are 1, 1, 0, 0. The inputs to MUX 228 are 1, 1, 1, 0. The inputsto MUX 230 are 1, 1, 1, 1. The following table shows the output of eachof the four MUXes based on the selector, which is the two leastsignificant bits (Isb) of the next address: MUX 224 MUX 226 MUX 228 MUX230 Selector output output output output 00 1 1 1 1 01 0 1 1 1 10 0 0 11 11 0 0 0 1

[0016] The output of each of the four MUXes 224, 226, 228, and 230 isone of the inputs to each of four AND gates 212, 214, 216, and 218respectively. Since the output of MUX 230 is always a 1, the MUX 230 maybe eliminated and replaced by wiring an input of 1 to AND gate 218. EachMUX output is ANDed together with one of the four jump bits of the uops116. In the example shown, the output of MUX 224 and the jump bit of thefirst uop (jump bit1) is input into AND gate 212. Likewise, the outputof MUX 226 and the jump bit of the second uop (jump bit2) is input intoAND gate 214, the output of MUX 228 and the jump bit of the third uop(jump bit3) is input into AND gate 216, and the output of MUX 230 andthe jump bit of the fourth uop (jump bit4) is input into AND gate 218.The outputs of the four AND gates 212, 214, 216, and 218 are input intoan OR gate 210 to determine if there was a jump executed 202. The jumppresent 200 and jump executed 202 are then compared to determine if thepredicted address 110 is correct. In one embodiment, the jump present200 and the jump executed 202 are compared using a XOR gate 206. Theoutput of the XOR gate 206 is the MUX select 118 that will select thepredicted address 110 as the next address if the predicted address 110is correct and will select the recovery address 112 as the next addressif the predicted address 110 is incorrect. In the example shown, the XORgate 206 will output a 0 when the jump present 200 and the jump executed202 have the same value, which indicates that the predicted address iscorrect. When the predicted address is incorrect, the jump present 200and the jump executed 202 will have different values, and the XOR gate206 will output a 1.

[0017] The recovery address 112 is determined using the next address114. The next address 114 is input into an adder 204. The adder 204 addsthe next address 114 to the number of uops per address line. In theexample implementation, there are four uops stored at an address line inmicrocode memory 102. Therefore, the adder 204 adds 4 to the nextaddress 114. Then, the two least significant bits (Isb) of the addressare zeroed out. In one embodiment, the two Isb are zeroed out by ANDingeach bit with a zero using two AND gates 220 and 222. After the numberof uops per line is added to the next address 114 and the two Isb arezeroed out, the result is a recovery address 112 that will be used asthe next address at which to access the microcode memory 102 if thepredicted address 110 is determined to be incorrect.

[0018] Referring to FIG. 3, a flow chart illustrating one embodiment ofthe method of the invention is provided. The method begins at step 300,where a next uop address is predicted. Then, the method continues tostep 302, where the predicted address is stored into memory. In oneembodiment, the predicted address is pre-programmed into a ROM. Then,the method continues to step 304, where the predicted address isretrieved from memory and used to obtain the next uops. Then, the methodcontinues to step 306, where the predicted address is corrected if theaddress was mispredicted.

[0019] An illustrative example of the method according to the inventionwill now be described. For purposes of illustration, assume that themicrocode ROM has the following data: at address 0, the uops in theaddress line are add, add, add, add; at address 4, the uops in theaddress line are jump to 9, add, add, add; at address 8, the uops in theaddress line are jump to 0, add, add, add; and at address 12, the uopsin the address line are add, add, add, add. Based on the uops in themicrocode, the predicted addresses are as follows: at address 0, thepredicted next address is 4; at address 4, the predicted next address is9 (since there is a uop that is a jump to 9); at address 8, thepredicted next address is 0 (since there is a uop that is a jump to 0);and at address 12, the predicted next address is 16.

[0020] On the first cycle, the microcode ROM is accessed at address 0and the uops read out of the ROM at that address line are add, add, add,add. Since none of the uops are jumps, the jump bits are all zero.Therefore, the jump present and the jump executed are both zero, and theMUX select is zero. With a MUX select of zero, the MUX 108 selects thepredicted address, which is 4, as the next address.

[0021] At address 4, the uops read out of the microcode ROM at thataddress line are jump to 9, add, add, add. Since the first uop is ajump, its jump bit is 1. The other three uops are adds, so their jumpbits are all 0. When the four jump bits are input into OR 208, theoutput is a 1, so the jump present 200 is equal to 1. The two leastsignificant bits of the next address are 00. With a selector of 00, thefour MUXes 224, 226, 228, and 230 will all output 1. When the jump bitof 1 from the first uop and the output 1 from MUX 224 is input into ANDgate 212, the output is 1. Therefore, the output of the OR gate 210 is a1, so the jump executed 202 is 1. Since the jump present and jumpexecuted are both 1, the MUX select is 0, and the predicted address of 9is selected as the next address.

[0022] At address 9, the uops read out of the microcode ROM at thataddress line are jump to 0, add, add, add. Since the first uop is ajump, the first jump bit is a 1. The other three uops are not jumps, sotheir jump bits are 0. Therefore, the jump present 200 is 1. Since theaddress is 9, the two least significant bits of the address are 01. Witha selector of 01, MUX 224 will output a 0 and the other three MUXes(226, 228, and 230) will each output a 1. When the MUX 224 output of 0and the first jump bit of 1 is input into AND 212, the output is 0. Whenthe MUX 226 output of 1 and the second jump bit of 0 is input into AND214, the output is 0. Likewise, when the MUX 228 output of 1 and thethird jump bit of 0 is input into AND 216, the output is 0, and when theMUX 230 output of 1 and the fourth jump bit of 0 is input into AND 218,the output is 0. Therefore, the output of all four AND gates will be 0,so the jump executed 202 will be 0. Since the jump present 200 is 1 andjump executed 202 is 0, the MUX select is 1, and the recovery address isselected as the next address. The recovery address is the address 9added with the number of uops per line (4) with the two leastsignificant bits zeroed out, which is equal to 12. Therefore, themicrocode ROM will be accessed at a next address of 12.

[0023] In one embodiment, registers are used to store the uops and thenext address to be used in the misprediction recovery logic. There maybe some latency in correcting the predicted address. Therefore, themicrocode ROM may be accessed at the predicted address of 0, and it maytake another cycle to correct the next address and access the microcodeROM at the correct next address of 12.

[0024] At address 12, the uops read out of the microcode ROM are add,add, add, add. Since there is no jump, all the jump bits are zero.Therefore, the jump present is zero and the jump executed is zero. TheMUX select is 0, and the MUX 108 selects the predicted address of 16 asthe next address at which to access the microcode ROM.

[0025] The above description of illustrated embodiments of theinvention, including what is described in the Abstract, is not intendedto be exhaustive or to limit the invention to the precise formsdisclosed. While specific embodiments of, and examples for, theinvention are described herein for illustrative purposes, variousequivalent modifications are possible within the scope of the invention,as those skilled in the relevant art will recognize.

[0026] These modifications can be made to the invention in light of theabove detailed description. The terms used in the following claimsshould not be construed to limit the invention to the specificembodiments disclosed in the specification and the claims. Rather, thescope of the invention is to be determined entirely by the followingclaims, which are to be construed in accordance with establisheddoctrines of claim interpretation.

What is claimed is:
 1. A method comprising: predicting a nextmicro-operation address; storing the predicted address into a firstmemory; retrieving the predicted address from the first memory;accessing a second memory at the retreived address to get a nextmicro-operation.
 2. The method of claim 1, wherein storing the predictedaddress comprises programming the address into a read-only memory. 3.The method of claim 1, further comprising determining whether themicro-operation address is correctly predicted.
 4. The method of claim3, further comprising correcting the predicted address if the address ismispredicted.
 5. The method of claim 4, wherein the next micro-operationindicates whether there is a jump present.
 6. The method of claim 5,wherein the next micro-operation comprises one or more jump bits.
 7. Themethod of claim 6, wherein determining whether the address is correctlypredicted comprises checking the jump bit of the next micro-operation.8. The method of claim 7, wherein the next micro-operation addresscomprises a plurality of bits.
 9. The method of claim 8, whereindetermining whether the address is correctly predicted further compriseschecking the two least significant bits of the next micro-operationaddress to determine if a jump was executed.
 10. The method of claim 9,wherein correcting the predicted address comprises zeroing out the twoleast significant bits of the next micro-operation address.
 11. Themethod of claim 1, further comprising storing the next micro-operationfor use in an instruction pipeline.
 12. The method of claim 11, whereinstoring the next micro-operation comprises writing the micro-operationinto a register.
 13. A system comprising: a first memory to storemicrocode, wherein the first memory is accessed at a next address to geta next micro-operation; a second memory to store predictedmicro-operation addresses; misprediction recovery logic coupled to thefirst memory to determine if the predicted address is correct and todetermine a recovery address; and a selector coupled to the firstmemory, the second memory, and the misprediction recovery, to selecteither the predicted address or the recovery address as the next addressat which to access the first memory based on the determination by themisprediction recovery logic as to whether the predicted address iscorrect.
 14. The system of claim 13, wherein the misprediction recoverylogic to determine if the predicted address is correct comprises themisprediction recovery logic to determine whether there is a jumppresent and whether a jump was executed.
 15. The system of claim 14,wherein each address comprises a plurality of bits.
 16. The system ofclaim 15, wherein the next micro-operation comprises at least one jumpbit.
 17. The system of claim 16, wherein the misprediction recoverylogic to determine whether there was a jump present comprises themisprediction recovery logic to check the jump bit of eachmicro-operation.
 18. The system of claim 17, wherein the mispredictionrecovery logic to determine whether there was a jump executed comprisesthe misprediction recovery logic to check the two least significant bitsof the next address.
 19. The system of claim 18, wherein themisprediction recovery logic to determine the recovery address comprisesthe misprediction recovery logic to zero out the two least significantbits of the next address.
 20. The system of claim 19, wherein themisprediction recovery logic to determine the recovery address furthercomprises the misprediction recovery logic to add the number ofmicro-operations per line to the next address.
 21. The system of claim13, further comprising a register coupled to the first memory to storethe next micro-operation.
 22. The system of claim 13, further comprisinga register coupled to the first memory to store the next address for useby the misprediction recovery logic.
 23. The system of claim 13, whereinthe selector is a multiplexer.
 24. A method comprising: predicting anext micro-operation address; determining a recovery address;determining whether the predicted address is correct; selecting betweenthe predicted address and the recovery address based on whether thepredicted address is correct; and accessing a memory with the selectedaddress to get the next micro-operation.
 25. The method of claim 24,further comprising storing the predicted address.
 26. The method ofclaim 25, wherein storing the predicted address comprises storing thepredicted address in a read-only memory.
 27. The method of claim 24,wherein determining whether the predicted address is correct comprisesdetermining whether there is a jump present and whether a jump wasexecuted.
 28. The method of claim 24, wherein the memory storesmicrocode.
 29. The method of claim 24, further comprising storing thenext micro-operation.
 30. The method of claim 24, further comprisingstoring the selected address.